Publication Type : Journal Article
Thematic Areas : Amrita Center for Cybersecurity Systems and Networks
Source : Communications in Computer and Information Science, Volume 335 CCIS, Trivandrum, p.215-224 (2012)
ISBN : 9783642341342
Keywords : DES, Digital storage, Field programmable gate arrays (FPGA), LFSR, Network security, performance, Scheduling, Security, Shift registers, Skew
Campus : Amritapuri
School : School of Engineering
Center : Cyber Security
Department : Electronics and Communication, cyber Security
Year : 2012
Abstract : In this paper, DES algorithm is implemented by applying pipelining concept to the key scheduling part. Using this implementation, it is possible to have the key length equal to data length; which further improves the security of the system, at the same time decaying the performance. This scenario is similar to that of one time pad. i.e, here key storage and transmission is going to occupy more area and power, degrading the performance of the system. The security vs performance trade off is analyzed for the circuit. Another solution is also introduced in this paper, i.e, the Linear Feedback Shift Registers(LFSRs). Using LFSR, it is possible to have different keys generated every clock cycles, improving the security of the system, at the same time we need to store or transmit the single seed of LFSR only. The design is implemented in Virtex 5 FPGA device using Xilinx 12.1 platform. An encryption rate of 35.5 gbits/S is obtained, which is almost the fastest among all other current implementations. The performance of the system in terms of area, power and timing is analyzed using the Synopsys tool. © 2012 Springer-Verlag.
Cite this Research Publication : P. Va Sruthi, Poornachandran, Pb, and Remya Ajai A. S., “Performance analysis and improvement using LFSR in the pipelined key scheduling section of DES”, Communications in Computer and Information Science, vol. 335 CCIS, pp. 215-224, 2012.