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FPGA Based Selective Harmonic Elimination Technique for Multilevel Inverter

Publication Type : Journal Article

Publisher : International Journal of Power Electronics and Drive Systems

Source : International Journal of Power Electronics and Drive Systems, Institute of Advanced Engineering and Science, Volume 9, Number 1, p.166-173 (2018)

Url : https://www.scopus.com/inward/record.uri?eid=2-s2.0-85042298290&doi=10.11591%2fijpeds.v9n1.pp166-173&partnerID=40&md5=0b26e56b7a5c5add3b4e36335beba9c2

Campus : Bengaluru

School : School of Engineering

Department : Electrical and Electronics

Year : 2018

Abstract : Harmonic elimination at the fundamental frequency is very much appropriate for high and medium range of power generation and applications. This paper considers a new technique for selective harmonic elimination (SHE), in which the total harmonic distortion (THD) is minimized when compared with that of the conventional one. With this technique, the harmonics at lower order are eliminated, which are more predominant than the higher ones. Cascaded H-Bridge inverter fed by a single DC is considered which is simulated with the switching angles generated by both the conventional method of SHE and the new method of SHE. The simulated results of the load voltage and the waveforms of the harmonic analysis are shown. The THD values are compared for the two techniques. The experimental results are also shown for the new technique. The switching angles are generated with the help of field programmable gated array (FPGA) in the hardware. The value of experimental THD of voltage is compared with that of simulated THD and the comparison prove that the results are satisfactory.

Cite this Research Publication : T. Porselvi, Dr. K. Deepa, and Muthu, R., “FPGA Based Selective Harmonic Elimination Technique for Multilevel Inverter”, International Journal of Power Electronics and Drive Systems, vol. 9, pp. 166-173, 2018.

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