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Design of static latch based comparator using power constrained optimization

Publication Type : Conference Paper

Publisher : 10th International Symposium on VLSI Design and Test

Source : 10th International Symposium on VLSI Design and Test (2010)

Campus : Amritapuri

School : School of Engineering

Department : Electronics and Communication

Year : 2010

Abstract :

Cite this Research Publication : Dr. Purushothaman A. and Parikh, C. D., “Design of static latch based comparator using power constrained optimization”, in 10th International Symposium on VLSI Design and Test, 2010.


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