Back close

FPGA Implementation of a Low Density Parity Check Code Decoder using Min Sum Algorithm

Publication Type : Conference Proceedings

Publisher : Trichy Engineering College

Source : National Conference on Emerging trends in Communication Engineering. Department of ECE, Trichy Engineering College, Trichy, 2009.

Campus : Coimbatore

School : School of Engineering

Department : Electronics and Communication

Year : 2009

Abstract :

Cite this Research Publication : R. .S and Ramesh S. R., “FPGA Implementation of a Low Density Parity Check Code Decoder using Min Sum Algorithm”, National Conference on Emerging trends in Communication Engineering. Department of ECE, Trichy Engineering College, Trichy, 2009.

Admissions Apply Now