M.Tech

Doing Ph.D :

Title: "Investigation into possible realization of Reconfigurable VLSI Systems through optimization in scheduling techniques."
Name of the Guide: Dr.T.R.Padmanabhan
Expected Date of Completion :March 2010

2005-ODD Semester (July – Dec, 2005) Courses Taught:

EC611 : Digital Design using hardware Modeling --4 hours
No of Students: 15
Digital Lab: 6 hours/week
No of Students: 64
EC690:VLSI Lab I;3 hours/week
No of Students:15

2006-EVEN Semester (Jan – May, 2006) Courses Taught:

Subject: EC654: CAD of VLSI circuits :4 hours/week
No of students:15
Analog Integrated Circuits
Lab: 6 hours/week
No of students :64

2006-ODD Semester (July – Dec, 2006) Courses Taught:

Subject: EC611:Digital Hardware Modeling:4 hours/week
No of students: 54 (common to M.Tech CVIP, Cyber Security, VLSI Design)
Digital Lab :9 hours/week
No of Students:96
VLSI Lab:3 Hours/ week,
No of Students:20

2007-EVEN Semester (Jan – May 2007) Courses Taught:

Subject: CAD of VLSI circuits :4 hours/week
Subject code: EC654
No of students: 20
Analog Integrated Circuits Lab: 6 hours/week
No of students: 64

B. Tech Projects Supervised (include student name, title & semester/yr)

1. Integer Linear Programming Model for scheduling for image processing application.Students: Divya CC, Pavitra Paularaj and Venkat Reddy.D -Final Year ECE A batch (2006-2007)
II. Improved FDS and FDS scheduling -A Performance comparison for 2-D image convolution. -Karthik, Navaneethan, Gowri Shankar Final Year ECE B batch (2006-2007).
III.Systolic architecture design for edge detection –Balaji -Final Year ECE A –batch(2005-2006)
IV. Comparison Force Directed Scheduling algorithms with functional pipelining and structural pipelining and for image processing –Prasanna, Prabhakar. Final Year ECE B Batch-(2005-2006 )

M. Tech Projects Supervised (include student name, title & semester/yr):

Mapping Image Processing Algorithms onto Systolic Architecture ,Kalyan Kumar, III &IV semester ,II Year , M.Tech VLSI Design ,(2006-2007) .

Publications / Patents

Digital Design through Verilog HDL, T.R.Padmanaabhan, B.Bala Tripura Sundari, IEEE-John Wiley -2003.
http://www.amrita.edu/ase/coimbatore/publications.htm

1. Chaired a session in national workshop in VLSI at Karpagam College ,Coimbatore.Gave a talk on Over view of VLSI Design in the above forum.
2.Participated in the organization of Amrita-TCS sangam -DSP Workshop organized by ECE department.
3.Reviewer for the B.Tech Projects.3.Convenor Class committee B.Tech ECE (2003-2007 )Batch, Amrita Vishwa Vidya Peetham.
4.Member –Board of Studies –PG (2005 November board of studies for Syllabus review )
5. Participated in the organization of Amrita-TCS sangam -DSP Workshop organized by ECE department.
6.Reviewer for the B.Tech Projects.
7.Convenor Class committee B.Tech ECE (2003-2007 )Batch, Amrita Vishwa Vidya Peetham.
8.Member –Board of Studies –PG (2005 November board of studies for Syllabus review )